When executed in the architecture register, the two CMP instructions are register-independent, so they can be executed at the same time, but the cpsr register has only one, so the two instructions can not be executed simultaneously. The result of the CMP instruction (*4) updates the NZCV flag in the cpsr register. Since the same registers are not used, the STR and LDR instructions can be executed simultaneously. The Cortex-A9 processor automatically replaces the physical registers and renames the STR instruction r0=p0/r1=p1 and the LDR instruction r0=p2/r2=p3. Because architectural registers use the same register (r0) for store and load data for different addresses, the LDR instruction cannot be executed until the STR instruction is completed. This section describes the operation of register renaming when successive STR (*2) and LDR (*3) instructions are executed in succession. The virtual flags (flg0-flg7) have copies of the cpsr flags NZCV, GE and Q bits.Ĭoding and debugging uses architecture registers and does not allow the use of physical registers.
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